The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique which is effectively applicable to enhancement of electric characteristics of semiconductor devices.
With respect to a semiconductor package (semiconductor device), conventionally, a problem relating to reflow cracks has been known. As a method for solving such a problem, a small tab structure which sets a size of tabs (chip mounting portions) to a value smaller than a size of semiconductor chips has been proposed. As one example of the small tab structure, a QFP (Quad Flat Package) having a small tab structure has been known.
Further, with respect to the semiconductor package having a small tab structure, to enhance electric characteristics such as characteristics which can cope with high frequency, there exists a semiconductor package which is required to have stabilization of ground/power source potential. For example, such a technique is disclosed in Japanese Unexamined Patent Publication No. Hei. 11(1999)-168169.
Japanese Unexamined Patent Publication No. Hei. 11(1999)-168169 discloses a technique that in a QFP having a small tab structure, ground/power source connecting portions which are supported by tab suspending leads (suspending leads) are provided, and by connecting pads (electrodes) of the semiconductor chip with the ground/power source connecting portions using wires, restrictions imposed on a pad layout is eliminated and, at the same time, the stability of ground/power source potential is enhanced.